`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:30:02 05/01/2014 
// Design Name: 
// Module Name:    boss_control 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module boss_control(		clk,slow_clk, rst,VS,
								
								Xpheonix, Ypheonix);
	input clk, rst,VS,slow_clk;
	output reg [9:0] Xpheonix, Ypheonix;	

	reg PheoIsMovingRight;		// is the pheonix moving right? false = moving left
	reg PheoIsMovingUp;			// false = moving down
	
	initial begin
		Xpheonix <= 64;
		Ypheonix <= 64;
	end


	always@(posedge clk ) begin
		if(!PheoIsMovingRight) begin
			if (!VS && slow_clk )	Xpheonix <= Xpheonix - 1'b1;
		end
		else begin
			if (!VS && slow_clk)	Xpheonix <= Xpheonix + 1'b1;
		end
	end

	always@(posedge clk) begin
		if (Xpheonix <= 35) begin
			PheoIsMovingRight <= 1'b1;
		end
		else if (Xpheonix + 95 >= 475) 
			PheoIsMovingRight <= 1'b0;
	end
	
	always@(posedge clk) begin
		if(!PheoIsMovingUp) begin
			if (!VS && slow_clk)	Ypheonix <= Ypheonix - 1'b1;
		end
		else begin
			if (!VS && slow_clk )	Ypheonix <= Ypheonix + 1'b1;
		end
	end

	always@(posedge clk) begin
		if (Ypheonix <= 35) begin
			PheoIsMovingUp <= 1'b1;
		end
		else if (Ypheonix >= 125) 
			PheoIsMovingUp <= 1'b0;
	end
	
	

endmodule
